Reference is now made to FIG. 1 which illustrates a circuit diagram of a prior art high voltage tolerant input buffer circuit 10. An input node 12 is configured to receive an input signal (IN) referenced to a relatively higher supply voltage. For example, the input signal may be referenced to a higher supply voltage of 5V, and may comprise a digital signal wherein the input signal is at 5V to represent a logic high data value and is at 0V to represent a logic low data value. The circuit 10, however, is powered from a relatively lower supply voltage (VDD). For example, the relatively lower supply voltage VDD may comprise 3.3V, 2.5V or 1.8V. Such a situation commonly occurs when interfacing an integrated circuit chip powered from the relatively lower supply voltage to receive input signals referenced to the relatively higher supply voltage.
A pair of series connected p-channel transistors 14 and 16 is coupled between a supply node 18 (configured to receive the relatively lower supply voltage VDD) and a ground reference node 20. The transistor 14 has a source terminal coupled to the supply node 18 and a drain terminal coupled to a control node 22. The transistor 16 has a source terminal coupled to the control node 22 and a drain terminal coupled to the ground reference node 20. The gate of the transistor 14 is coupled to receive a bias voltage (Vbiasp) generated by an appropriate bias voltage generator (not shown, but well known to those skilled in the art). The transistor 14 accordingly functions as a current source and the transistor 16 functions as a source follower.
A pair of series connected n-channel transistors 24 and 26 is coupled between the supply node 18 (configured to receive the relatively lower supply voltage VDD) and the ground reference node 20. The transistor 24 has a drain terminal coupled to the supply node 18 and a source terminal coupled to a control node 32. The transistor 26 has a drain terminal coupled to the control node 32 and a source terminal coupled to the ground reference node 20. The gate of the transistor 26 is coupled to receive a bias voltage (Vbiasn) generated by an appropriate bias voltage generator (not shown, but well known to those skilled in the art). The transistor 26 accordingly functions as a current source and the transistor 24 functions as a source follower.
An n-channel transistor 40 and p-channel transistor 42 are coupled in series between the input node 12 and an output node 44. The transistor 40 has a source terminal coupled to the input node and a drain terminal coupled to an intermediate node 46. The transistor 42 has a drain terminal coupled to an intermediate node 46 and a source terminal coupled to the output node 44. The gate of transistor 40 is coupled to the control node 22 and the gate of transistor 42 is coupled to the control node 32. The gate of transistor 16 is coupled to the intermediate node 46. The gate of transistor 24 is coupled to the output node 44.
The circuit comprised of transistors 14, 16 and 40 forms a first clipping circuit designed to clip positive voltages on the input signal received at input node 12. The first clipping circuit operates as follows: as the input signal IN increases in voltage, there is an increase in the gate voltage of transistor 16. The voltage at the control node 22 leads the voltage at the input node 12 by a threshold voltage Vt of the transistor 16.
Saturation occurs as the voltage at the input node 12 approaches VDD. The stress across transistor 40 is accordingly managed and the input signal is clipped to produce an output signal OUT with a voltage no higher than VDD−Vt of the transistor 40.
The circuit comprised of transistors 24, 26 and 42 forms a second clipping circuit designed to clip negative voltages on the input signal propagated to intermediate node 46. The second clipping circuit operates as follows: as the input signal decreases in voltage, there is a decrease in the gate voltage of transistor 24. The voltage at the control node 32 follows the voltage at the output node 44 by a threshold voltage Vt of the transistor 24. Saturation occurs as the voltage at the output node 44 approaches 0V. The stress across transistor 42 is accordingly managed and the input signal is clipped to produce an output signal OUT with a voltage no lower than Vt of transistor 42.
The control nodes 22 and 32 vary with changes in the input signal IN within an input signal range of Vt to VDD−Vt. If the input signal exceeds VDD−Vt, the output signal is clamped to VDD−Vt. If the input signal is less than Vt, the output signal is clamped to Vt. The circuit 10 accordingly functions to control the signal (OUT) at the output node 44 in the range of Vt to VDD−Vt even though the input signal (IN) may range from a few negative volts to the relatively higher supply voltage (for example, 5V).
Circuits for other high voltage tolerant input buffers are well known in the art.
Many input tolerant buffer circuits, however, suffer from concerns over maintaining linearity of output characteristic over a specified common mode range while still providing for voltage clipping. There is a need in the art for a tolerant input buffer circuit that can address the foregoing and other problems.